74V1T126
SINGLE BUS BUFFER (3-STATE)
PRELIMINARY DATA
October 1999
n HIGH SPEED: tPD = 3.8 ns (TYP.) at VCC =5V
n LOW POWER DISSIPATION:
ICC =1 µA (MAX.) at TA =25
o
C
n COMPATIBLEWITH TTL OUTPUTS:
VIH =2V(MIN),VIL = 0.8V(MAX)
n POWERDOWN PROTECTIONON INPUT
n SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=IOL = 8 mA (MIN)
n BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
n OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
n IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V1T126 is an advanced high-speed
CMOS SINGLE BUS BUFFER fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
3-STATE control input G has to be set LOW to
place the output into the high impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
PIN CONNECTION AND IEC LOGIC SYMBOLS

S
(SOT23-5L)
C
(SC-70)
ORDER CODE:
74V1T126S 74V1T126C
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