© 2005 Fairchild Semiconductor Corporation DS011614 www.fairchildsemi.com
June 1993
Revised April 2005
7
4
L
VX27
3

Low V
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74LVX273
Low Voltage Octal D-Type Flip-Flop
General Description
The LVX273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) input load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements. The inputs tolerate up to 7V allowing
interface of 5V systems to 3V systems.
Features
a73 Input voltage translation from 5V to 3V
a73 Ideal for low power/low noise 3.3V applications
a73 Guaranteed simultaneous switching noise level and
dynamic threshold performance

Ordering Code:
Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth Table
H c32 HIGH Voltage Level X c32 Immaterial
L c32 LOW Voltage Level c17 c32 LOW-to-HIGH Transition
Order Number Package Number Package Description
74LVX273M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVX273SJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
D
0
–D
7
Data Inputs
MR Master Reset
CP Clock Pulse Input
Q
0
–Q
7
Data Outputs
Operating Mode Inputs Outputs
MR CP D
n
Q
n
Reset (Clear) L X X L
Load '1' H c17 HH
Load '0' H c17 LL