1/10February 2003
a73 HIGH SPEED:
f
MAX
= 160 MHz (TYP.) at V
CC
=3V
a73 5V TOLERANT INPUTS
a73 POWER DOWN PROTECTION ON INPUTS
a73 INPUT VOLTAGE LEVEL:
V
IL
=0.8V,V
IH
=2VatV
CC
=3V
a73 LOW POWER DISSIPATION:
I
CC
=4µA (MAX.) at T
A
=25°C
a73 LOW NOISE:
V
OLP
=0.3V(TYP.)atV
CC
=3.3V
a73 SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
|=I
OL
=4mA(MIN)atV
CC
=3V
a73 BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
a73 PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16373
a73 IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVX16374 is a low voltage CMOS 16 BIT
D-TYPE FLIP-FLOP with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
These 16 bit D-TYPE flip-flop is controlled by two
clock inputs (CK) and two output enable inputs
(nOE). The device can be used as two 8-bit
flip-flops or one 16-bit flip-flop.On the positive
transition of the clock, the Q outputs will be set to
the logic state that were setup at the D inputs.
While the (OE) input is low, the outputs will be in
a normal logic state (high or low logic level); while
OEis high, the outputs will be in a high impedance
state.The output control does not affect the inter-
nal operation of flip-flops; that is, the old data can
be retained or the new data can be entered even
while the outputs are off.Power down protection is
provided on all inputs and 0 to 7V can be accepted
on inputs with no regard to the supply voltage.This
device can be used to interface 5V to 3V. All in-
puts and outputs are equipped with protection cir-
cuits against static discharge, giving them 2KV
ESD immunity and transient excess voltage.
74LVX16374
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP FLOP (3-STATE)
WITH 5V TOLERANT INPUTS
ORDER CODES
PACKAGE TUBE T & R
TSSOP 74LVX16374TTR
TSSOP
PIN CONNECTION