© 2003 Fairchild Semiconductor Corporation DS012158 www.fairchildsemi.com
October 1996
Revised December 2003
7
4
L
VX1
1
2
Low
V
o
l
t
a
g
e Dual
J-
K Fl
i
p
-Fl
ops
w
i
th
Prese
t
and Cl
ear
74LVX112
Low Voltage Dual J-K Flip-Flops with Preset and Clear
General Description
The LVX112 is a dual J-K Flip-Flop where each flip-flop has
independent inputs (J, K, PRESET, CLEAR, and CLOCK)
and outputs (Q, Q). These devices are edge sensitive and
change states synchronously on the negative going transi-
tion of the clock pulse. Triggering occurs at a voltage level
of the clock and is not directly related to the transition time.
Clear and Preset are independent of the clock and are
accomplished by a low logic level on the corresponding
input. The J and K inputs can change when the clock is in
either state without affecting the flip-flop, provided that they
are in the desired state during the recommended setup and
hold times relative to the falling edge of the clock.
The inputs tolerate voltages up to 7V allowing the interface
of 5V systems to 3V systems.
Features
a73 Input voltage level translation from 5V–3V
a73 Ideal for low power/low noise 3.3V applications

Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74LVX112M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LVX112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVX112MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
J
1
, J
2
, K
1
, K
2
Data Inputs
CLK
1
, CLK
2
Clock Pulse Inputs (Active Falling edge)
CLR
1
, CLR
2
Direct Clear Inputs (Active LOW)
PR
1
, PR
2
Direct Preset Inputs (Active LOW)
Q
1
, Q
2
, Q
1
, Q
2