Preliminary
© 2000 Fairchild Semiconductor Corporation DS012447 www.fairchildsemi.com
May 2000
Revised May 2000
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74LVTH16500
Low Voltage 18-Bit Universal Bus Transceivers
with 3-STATE Outputs (Preliminary)
General Description
The LVTH16500 is an 18-bit universal bus transceiver
combining D-type latches and D-type flip-flops to allow
data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs.
The LVTH16500 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
The transceiver is designed for low voltage (3.3V) V
CC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH16500 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining low
power dissipation.
Features
a73 Input and output interface capability to systems at
5V V
CC
a73 Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
a73 Live insertion/extraction permitted
a73 Power Up/Down high impedance provides glitch-free
bus loading
a73 Outputs source/sink −32 mA/+64 mA
a73 Functionally compatible with the 74 series 16500
a73 Latch-up performance exceeds 500 mA

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix “X” to the ordering code.
Order Number Package Number Package Description
74LVTH16500MEA MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
74LVTH16500MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide