74LVT322373
器件描述：Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs and 25з Series Resistors in the Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：161.08KB，共6页
Sponsor by e络盟器件资料摘要：
© 2002 Fairchild Semiconductor Corporation DS500742 www.fairchildsemi.com
May 2002
Revised May 2002
7
4
L
V
T3
22373
• 74L
VTH322373
Low
V
o
l
t
ag
e 32-
Bit
T
r
anspar
ent
Latc
h wi
th
3-ST
A
T
E Out
puts
and
25
Ω
Seri
es
Res
i
st
ors in the
O
u
tp
uts
74LVT322373 74LVTH322373
Low Voltage 32-Bit Transparent Latch
with 3-STATE Outputs
and 25Ω Series Resistors in the Outputs
General Description
The LVT322373 and LVTH322373 contain thirty-two non-
inverting latches with 3-STATE outputs and are intended
for bus oriented applications. The device is byte controlled.
The flip-flops appear transparent to the data when the
Latch Enable (LE) is HIGH. When LE is LOW, the data that
meets the setup time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the outputs are in a high impedance state.
The LVTH322373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These latches are designed for low voltage (3.3V) V
CC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVT322373 and
LVTH322373 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Features
a73 Input and output interface capability to systems at
5V V
CC
a73 Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH322373),
also available without bushold feature (74LVT322373)
a73 Live insertion/extraction permitted
a73 Power Up/Down high impedance provides glitch-free
bus loading
a73 Outputs include equivalent series resistance of 25Ω to
make external termination resistors unnecessary and
reduce overshoot and undershoot
a73 ESD performance:
Human-body model > 2000V
Machine model > 200V
Charged-device model > 1000V
a73 Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Note 1: Ordering Code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Order Number Package Number Package Description
74LVT322373G
(Note 1) (Note 2)
BGA96A
(Preliminary)
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVTH322373G
(Note 1) (Note 2)
BGA96A 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
May 2002
Revised May 2002
7
4
L
V
T3
22373
• 74L
VTH322373
Low
V
o
l
t
ag
e 32-
Bit
T
r
anspar
ent
Latc
h wi
th
3-ST
A
T
E Out
puts
and
25
Ω
Seri
es
Res
i
st
ors in the
O
u
tp
uts
74LVT322373 74LVTH322373
Low Voltage 32-Bit Transparent Latch
with 3-STATE Outputs
and 25Ω Series Resistors in the Outputs
General Description
The LVT322373 and LVTH322373 contain thirty-two non-
inverting latches with 3-STATE outputs and are intended
for bus oriented applications. The device is byte controlled.
The flip-flops appear transparent to the data when the
Latch Enable (LE) is HIGH. When LE is LOW, the data that
meets the setup time is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the outputs are in a high impedance state.
The LVTH322373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These latches are designed for low voltage (3.3V) V
CC
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVT322373 and
LVTH322373 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
Features
a73 Input and output interface capability to systems at
5V V
CC
a73 Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH322373),
also available without bushold feature (74LVT322373)
a73 Live insertion/extraction permitted
a73 Power Up/Down high impedance provides glitch-free
bus loading
a73 Outputs include equivalent series resistance of 25Ω to
make external termination resistors unnecessary and
reduce overshoot and undershoot
a73 ESD performance:
Human-body model > 2000V
Machine model > 200V
Charged-device model > 1000V
a73 Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Note 1: Ordering Code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Order Number Package Number Package Description
74LVT322373G
(Note 1) (Note 2)
BGA96A
(Preliminary)
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVTH322373G
(Note 1) (Note 2)
BGA96A 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide