74LVQ74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

February 1999
n HIGH SPEED:
fMAX = 250 MHz (TYP.) at VCC =3.3V
n COMPATIBLEWITH TTL OUTPUTS
n LOW POWER DISSIPATION:
ICC =2 µA (MAX.) at TA =25
o
C
n LOW NOISE:
VOLP = 0.2 V (TYP.) at VCC =3.3V
n 75Ω TRANSMISSIONLINE DRIVING
CAPABILITY
n SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
|=I
OL
= 12 mA (MIN)
n PCI BUS LEVELSGUARANTEED AT 24mA
n BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
n OPERATING VOLTAGE RANGE:
V
CC
(OPR)= 2V to 3.6V (1.2VData Retention)
n PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 74
n IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ74 is a low voltage CMOS DUAL
D-TYPE FLIP FLOP WITH PRESET AND CLEAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.It is ideal for low power and low noise
3.3V applications.
A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of
the clock pulse.
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriateinput.
It has better speed performance at 3.3V than 5V
LSTTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ74M 74LVQ74T
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