74LVQ574
OCTAL D-TYPE FLIP FLOP
WITH 3 STATE OUTPUTS NON INVERTING

February 1999
n HIGH SPEED:
fMAX = 180 MHz (TYP.) at VCC =3.3V
n COMPATIBLEWITH TTL OUTPUTS
n LOW POWER DISSIPATION:
ICC =4 µA (MAX.) at TA =25
o
C
n LOW NOISE:
VOLP = 0.5 V (TYP.) at VCC =3.3V
n 75Ω TRANSMISSIONLINE DRIVING
CAPABILITY
n SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=IOL = 12 mA (MIN)
n PCI BUS LEVELSGUARANTEED AT 24 mA
n BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
n OPERATING VOLTAGE RANGE:
VCC (OPR)= 2V to 3.6V (1.2VData Retention)
n PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
n IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ574 is a low voltage CMOS OCTAL
D-TYPE FLIP FLOP with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.It is ideal for low power and low noise
3.3V applications.
These 8 bit D-Type flip-flops are controlled by a
clock input (CK) and an output enable input (OE).
On the positive transition of the clock, the Q
outputs will be set to logic state that were setup
at the D inputs.
While the (OE) input is low, the 8 outputs will be
in al normal logic state (high or low logic level)
and while high level, the outputs will be in a high
impedance state.
The output control does not affect the internal
operation of flip flop, that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumpion.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES :
74LVQ574M 74LVQ574T
M
(Micro Package)
T
(TSSOP Package)
1/10