74LVQ573
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS NON INVERTING

February 1999
n HIGH SPEED: t
PD
= 5 ns (TYP.) at V
CC
= 3.3V
n COMPATIBLEWITH TTL OUTPUTS
n LOW POWER DISSIPATION:
ICC =4 µA (MAX.) at TA =25
o
C
n LOW NOISE:
V
OLP
= 0.5 V (TYP.) at V
CC
=3.3V
n 75Ω TRANSMISSIONLINE DRIVING
CAPABILITY
n SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=IOL = 24 mA (MIN)
n PCI BUS LEVELSGUARANTEED AT 24mA
n BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
n OPERATING VOLTAGE RANGE:
VCC (OPR)= 2V to 3.6V (1.2VData Retention)
n PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
n IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ573 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. It is ideal for low power and low
noise 3.3V applications.
These 8 bit D-Type flip-flops are controlled by a
latch enable input (LE) and an output enable
input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be
in a normal logic state (high or low logic level)
and while high level the outputs will be in a high
impedance state.
It has better speed performance at 3.3V than 5V
LSTTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES :
74LVQ573M 74LVQ573T
M
(Micro Package)
T
(TSSOP Package)
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