74LVQ02
器件描述：QUAD 2-INPUT NOR GATE
器件厂商：STMICROELECTRONICS [STMicroelectronics]
厂商主页：http://www.st.com/
文件大小：56.53KB，共8页
Sponsor by e络盟器件资料摘要：
74LVQ02
QUAD 2-INPUT NOR GATE
February 1999
PIN CONNECTION AND IEC LOGIC SYMBOLS
n HIGH SPEED: t
PD
= 5 ns (TYP.) at V
CC
= 3.3V
n COMPATIBLEWITH TTL OUTPUTS
n LOW POWER DISSIPATION:
I
CC
=2 µA (MAX.) at T
A
=25
o
C
n LOW NOISE:
V
OLP
= 0.3 V (TYP.) at V
CC
=3.3V
n 75Ω TRANSMISSIONLINE DRIVING
CAPABILITY
n SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=IOL = 12 mA (MIN)
n PCI BUS LEVELSGUARANTEED AT 24mA
n BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
n OPERATING VOLTAGE RANGE:
VCC (OPR)= 2V to 3.6V (1.2VData Retention)
n PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 02
n IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ02 is a low voltage CMOS QUAD
2-INPUT NOR GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
ORDER CODES :
74LVQ02M 74LVQ02T
M
(Micro Package)
T
(TSSOP Package)
1/8
QUAD 2-INPUT NOR GATE
February 1999
PIN CONNECTION AND IEC LOGIC SYMBOLS
n HIGH SPEED: t
PD
= 5 ns (TYP.) at V
CC
= 3.3V
n COMPATIBLEWITH TTL OUTPUTS
n LOW POWER DISSIPATION:
I
CC
=2 µA (MAX.) at T
A
=25
o
C
n LOW NOISE:
V
OLP
= 0.3 V (TYP.) at V
CC
=3.3V
n 75Ω TRANSMISSIONLINE DRIVING
CAPABILITY
n SYMMETRICAL OUTPUT IMPEDANCE:
|IOH|=IOL = 12 mA (MIN)
n PCI BUS LEVELSGUARANTEED AT 24mA
n BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
n OPERATING VOLTAGE RANGE:
VCC (OPR)= 2V to 3.6V (1.2VData Retention)
n PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 02
n IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The LVQ02 is a low voltage CMOS QUAD
2-INPUT NOR GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
technology.It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
ORDER CODES :
74LVQ02M 74LVQ02T
M
(Micro Package)
T
(TSSOP Package)
1/8