1/11May 2003
a73 HIGH SPEED: t
PD
= 9ns (MAX.) at V
CC
=3V
a73 LOW POWER DISSIPATION:
I
CC
=20µA(MAX)atV
CC
=3.6V T
A
=85°C
a73 TTL COMPATIBLE INPUTS
V
IH
=2V (MIN) V
IL
=0.8(MAX)
a73 OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 3.0V to 3.6V
a73 A PORT HAVE STANDARD 4mA TOTEM
POLE OUTPUT
a73 B PORT HIGH DRIVE SOURCE/SINK
CAPABILITY OF 14mA
a73 SUPPORT IEEE STD 1284-I (LEVEL 1 TYPE)
AND IEEE STD 1284-II (LEVEL 2 TYPE) FOR
BIDIRECTIONAL PARALLEL
COMMUNICATIONS BETWEEN PERSONAL
COMPUTER ANT PRINTING PERIPHERALS
a73 TRANSLATION CAPABILITY ALLOW
OUTPUTSONCABLESIDETOINTERFACE
WITH 5V SIGNAL
a73 PULL-UP RESISTOR INTEGRATED ON ALL
OPEN-DRAIN OUTPUT ELIMINATE THE
NEED FOR DISCRETE RESISTOR
a73 REPLACE THE FUNCTION OF TWO
74LVC1284 DEVICES
DESCRIPTION
The 74LVC161284 contains eight high speed non
inverting bidirectional buffers and eleven control/
status non-inverting buffers with open drain
outputs fabricated in silicon gate C
2
MOS
technology. It’s intended to provide a standard
signaling method for a bi-direction parallel
peripheral in an Extended Capabilities Port Mode
(ECP). The HD (Active HIGH) input pin enables
the Cable port to switch from Open Drain to a high
drive totem pole output, capable of sourcing 14mA
on all thirteen buffer and 84mA on PERI LOGIC
OUTPUT buffer. The DIR input determines the
direction of data flow on the bidirectional buffers.
DIR (Active HIGH) enables data flow from A port
to B port. DIR (Active LOW) enables data flow
from B port to A port. It is available in the
commercial temperature range.
74LVC161284
LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER
ORDER CODES
PACKAGE TUBE T & R
TSSOP 74LVC161284TTR
TSSOP
PIN CONNECTION