© 2000 Fairchild Semiconductor Corporation DS006381 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS90 Decade and Binar
y
Count
ers
DM74LS90
Decade and Binary Counters
General Description
Each of these monolithic counters contains four master-
slave flip-flops and additional gating to provide a divide-by-
two counter and a three-stage binary counter for which the
count cycle length is divide-by-five for the DM74LS90.
All of these counters have a gated zero reset and the
DM74LS90 also has gated set-to-nine inputs for use in
BCD nine’s complement applications.
To use their maximum count length (decade or four bit
binary), the B input is connected to the Q
A
output. The
input count pulses are applied to input A and the outputs
are as described in the appropriate truth table. A symmetri-
cal divide-by-ten count can be obtained from the
DM74LS90 counters by connecting the Q
D
output to the A
input and applying the input count to the B input which
gives a divide-by-ten square wave at output Q
A
.
Features
a73 Typical power dissipation 45 mW
a73 Count frequency 42 MHz

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Reset/Count Truth Table
Order Number Package Number Package Description
DM74LS90M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS90N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Reset Inputs Output
R0(1) R0(2) R9(1) R9(2) Q
D
Q
C
Q
B
Q
A
H H L X LLLL
H H X L LLLL
XXHHHLLH
X L X L COUNT
L X L X COUNT
L X X L COUNT
X L L X COUNT