© 2000 Fairchild Semiconductor Corporation DS009814 www.fairchildsemi.com
October 1988
Revised March 2000
DM74LS573

Octa
l D-T
ype Latch wit
h

3
-
ST
A
T
E
Outpu
t
s
DM74LS573
Octal D-Type Latch with 3-STATE Outputs
General Description
The DM74LS573 is a high speed octal latch with buffered
common Latch Enable (LE) and buffered common Output
Enable (OE) inputs.
This device is functionally identical to the DM74LS373, but
has different pinouts.
Features
a73 Inputs and outputs on opposite sides of package allow-
ing easy interface with microprocessors
a73 Useful as input or output port for microprocessors
a73 Functionally identical to DM74LS373
a73 Input clamp diodes limit high speed termination effects
a73 Fully TTL and CMOS compatible

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
V
CC
= Pin 20
GND = Pin 10
Connection Diagram
Pin Descriptions Function Tables
L = LOW State
H = HIGH State
X = Don't Care
Z = High Impedance State
Q
O
= Previous Condition of O
Order Number Package Number Package Description
DM74LS573WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS573N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
D0–D7 Data Inputs
LE Latch Enable Input (Active HIGH)
OE 3-STATE Output Enable Input (Active LOW)
O0–O7 3-STATE Latch Outputs
Output Latch
D
Output
Enable Enable O
LHHH
LHLL
LLXQ
O
HX Z