© 2000 Fairchild Semiconductor Corporation DS006369 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS51
Dual
2-
Wi
de 2-
I
nput,
2-
Wi
de
3-I
nput
AND-OR-I
NVERT Gat
e
DM74LS51
Dual 2-Wide 2-Input, 2-Wide 3-Input
AND-OR-INVERT Gate
General Description
This device contains two independent combinations of
gates each of which performs the logic AND-OR-INVERT
function. Each package contains one 2-wide 2-input and
one 2-wide 3-input AND-OR-INVERT gates.

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
Order Number Package Number Package Description
DM74LS51M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS51N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Y1 = (A1) (B1) (C1) + (D1) (E1) (F1)
Inputs Output
A1 B1 C1 D1 E1 F1 Y1
HHHXXX L
XXXHHH L
Other Combinations H
Y2 = ((A2) (B2) + (C2) (D2))
Inputs Output
A2 B2 C2 D2 Y2
HHXXL
XXHH
Other combinations H