LOGIC DIAGRAM (ONE HALF SHOWN)
C0077C0083
C0067C0080
C0077C0082
C0052
C0049C0050
C0049
C0049C0053
C0050
C0049C0052
C0075
C0067
C0068
C0074
C0083
C0068
C0081
C0075
C0067
C0068
C0074
C0081
C0075
C0067
C0068
C0074
C0083
C0068
C0081
C0051 C0081
C0048
C0049C0051 C0053 C0081
C0049
C0049C0049 C0054 C0081
C0050
C0049C0048 C0055 C0081
C0051
C0057
C0075
C0067
C0068
C0074
C0081
TRUTH TABLE
C0067C0080
5-563
FAST AND LS TTL DATA
DUAL DECADE COUNTER
The SN54/74LS490 contains a pair of high-speed 4-stage ripple counters.
Each half of the SN54/74LS490 has individual Clock, Master Reset and Mas-
ter Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code.
• Dual Version of SN54/74LS490
• Individual Asynchronous Clear and Preset to 9 for Each Counter
• Count Frequency — Typically 65 MHz
• Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
C0049C0052 C0049C0051 C0049C0050 C0049C0049 C0049C0048 C0057
C0049 C0050 C0051 C0052 C0053 C0054 C0055
C0049C0054 C0049C0053
C0056
C0086
C0067C0067
C0067C0080
C0097
C0067C0080
C0098
C0077C0082
C0098
C0081
C0048C0098
C0077C0083
C0098
C0081
C0050C0098
C0081
C0049C0098
C0081
C0051C0098
C0077C0082
C0097
C0081
C0048C0097
C0077C0083
C0097
C0081
C0049C0097
C0081
C0050C0097
C0081
C0051C0097
C0071C0078C0068
PIN NAMES LOADING (Note a)
HIGH LOW
MS Master Set (Set to 9) Input 0.5 U.L. 0.25 U.L.
MR Master Reset 0.5 U.L. 0.25 U.L.
CP Clock Input (Active LOW Going Edge) 1.5 U.L. 1.5 U.L.
Q
0
–Q
3
Counter Outputs (Note b) 10 U.L. 5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) Temperature Ranges.
OUTPUTS
COUNT Q
3
Q
2
Q
1
Q
0
0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
5 L H L H
6 L H H L
7 L H H H
8 H L L L
9 H L L H
SN54/74LS490
DUAL DECADE COUNTER
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
16
1
D SUFFIX
SOIC
CASE 751B-03