© 2000 Fairchild Semiconductor Corporation DS006434 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS393
Dual
4-
Bit
Bi
nary
Count
er
DM74LS393
Dual 4-Bit Binary Counter
General Description
Each of these monolithic circuits contains eight master-
slave flip-flops and additional gating to implement two indi-
vidual four-bit counters in a single package. The
DM74LS393 comprises two independent four-bit binary
counters each having a clear and a clock input. N-bit binary
counters can be implemented with each package providing
the capability of divide-by-256. The DM74LS393 has paral-
lel outputs from each counter stage so that any submultiple
of the input count frequency is available for system-timing
signals.
Features
a73 Dual version of the popular DM74LS93
a73 DM74LS393 dual 4-bit binary counter with individual
clocks
a73 Direct clear for each 4-bit counter
a73 Dual 4-bit versions can significantly improve system
densities by reducing counter package count by 50%
a73 Typical maximum count frequency 35 MHz
a73 Buffered outputs reduce possibility of collector commu-
tation

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
Counter Sequence (Each Counter)
H = HIGH Logic Level
L = LOW Logic Level
Order Number Package Number Package Description
DM74LS393M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS373N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Count
Outputs
Q
D
Q
C
Q
B
Q
A
0 LLLL
1 LLLH
2LLHL
3L H
4LHLL
5L LH
6LHHL
7 LHHH
8 HLLL
9HLLH
10 HLHL
11 H L H H
12 H H L L
13 H H L H
14 HHHL
15 HHHH