© 2000 Fairchild Semiconductor Corporation DS006433 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS390
Dual
4-
Bit
Deca
de Count
er
DM74LS390
Dual 4-Bit Decade Counter
General Description
Each of these monolithic circuits contains eight master-
slave flip-flops and additional gating to implement two indi-
vidual four-bit counters in a single package. The
DM74LS390 incorporates dual divide-by-two and divide-
by-five counters, which can be used to implement cycle
lengths equal to any whole and/or cumulative multiples of 2
and/or 5 up to divide-by-100. When connected as a bi-qui-
nary counter, the separate divide-by-two circuit can be
used to provide symmetry (a square wave) at the final out-
put stage. The DM74LS390 has parallel outputs from each
counter stage so that any submultiple of the input count fre-
quency is available for system-timing signals.
Features
a73 Dual version of the popular DM74LS90
a73 DM74LS390...individual clocks for A and B flip-flops
provide dual ÷ 2 and ÷ 5 counters
a73 Direct clear for each 4-bit counter
a73 Dual 4-bit version can significantly improve system den-
sities by reducing counter package count by 50%
a73 Typical maximum count frequency...35 MHz
a73 Buffered outputs reduce possibility of collector commu-
tation

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number Package Number Package Description
DM74LS390M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS390N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide