© 2000 Fairchild Semiconductor Corporation DS006363 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS38 Quad 2-I
nput NAND
Buff
er wit
h

Open-
Coll
ect
or O
u
tput
s
DM74LS38
Quad 2-Input NAND Buffer with Open-Collector Outputs
General Description
This device contains four independent gates, each of which
performs the logic NAND function. The open-collector out-
puts require external pull-up resistors for proper logical
operation.
Pull-Up Resistor Equations
Where: N
1
(I
OH
) = total maximum output high current
for all outputs tied to pull-up resistor
N
2
(I
IH
) = total maximum input high current for
all inputs tied to pull-up resistor
N
3
(I
IL
) = total maximum input low current for
all inputs tied to pull-up resistor

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
Y = AB
H = HIGH Logic Level
L = LOW Logic Level
Order Number Package Number Package Description
DM74LS38M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS38SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS38N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Output
ABY
LLH
LH
HLH
HHL