© 2000 Fairchild Semiconductor Corporation DS009831 www.fairchildsemi.com
October 1988
Revised March 2000
DM74LS377

Octa
l D-T
ype Fli
p
-Fl
op w
i
t
h

Comm
on Enabl
e
and Clo
c
k
DM74LS377
Octal D-Type Flip-Flop with Common Enable and Clock
General Description
The DM74LS377 is an 8-bit register built using advanced
low power Schottky technology. This register consists of
eight D-type flip-flops with a buffered common clock and a
buffered common input enable. The device is packaged in
the space-saving (0.3 inch row spacing) 20-pin package.
Features
a73 8-bit high speed parallel registers
a73 Positive edge-triggered D-type flip-flops
a73 Fully buffered common clock and enable inputs

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
V
CC
= Pin 20
GND = Pin 10
Pin Descriptions
Connection Diagram
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Order Number Package Number Package Description
DM74LS377WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS377N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
E Enable Input (Active LOW)
D0–D7 Data Inputs
CP Clock Pulse Input (Active Rising Edge)
Q0–Q7 Flip-Flop Outputs
Inputs Output
E CP D
n
Q
n
H X X No Change
L c17 HH
L c17 LL