© 2000 Fairchild Semiconductor Corporation DS009826 www.fairchildsemi.com
October 1988
Revised March 2000
DM74LS298

Quad 2-Por
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Regist
er Mult
ipl
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S
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DM74LS298
Quad 2-Port Register Multiplexer with Storage
General Description
The DM74LS298 is a quad 2-port register. It is the logical
equivalent of a quad 2-input multiplexer followed by a quad
4-bit edge-triggered register. A Common Select input
selects between two 4-bit input ports (data sources). The
selected data is transferred to the output register synchro-
nous with the HIGH-to-LOW transition of the Clock input.
Features
a73 Select from two data sources
a73 Fully edge-triggered operation
a73 Typical power dissipation of 65 mW

Ordering Code:
Logic Symbol
V
CC
= Pin 16
GND = Pin 8
Pin Descriptions
Connection Diagram
Truth Table
l = LOW Voltage Level one setup time prior to the HIGH-to-LOW clock
transition.
h = HIGH Voltage Level one setup time prior to the HIGH-to-LOW clock
transition.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Order Number Package Number Package Description
DM74LS298N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
S Common Select Inputs
CP Clock Pulse Input (Active Falling Edge)
I0
a
, I0
d
Source 0 Data Inputs
I1
a
, I1
d
Source 1 Data Inputs
Q
a
, Q
d
Flip-Flip Outputs
Inputs Output
SI0
x
I1
x
Q
x
ll X L
lh H
hX l L
h