© 2000 Fairchild Semiconductor Corporation DS006407 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS194
A

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DM74LS194A
4-Bit Bidirectional Universal Shift Register
General Description
This bidirectional shift register is designed to incorporate
virtually all of the features a system designer may want in a
shift register; they feature parallel inputs, parallel outputs,
right-shift and left-shift serial inputs, operating-mode-con-
trol inputs, and a direct overriding clear line. The register
has four distinct modes of operation, namely:
Parallel (broadside) load
Shift right (in the direction Q
A
toward Q
D
)
Shift left (in the direction Q
D
toward Q
A
)
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying
the four bits of data and taking both mode control inputs,
S0 and S1, HIGH. The data is loaded into the associated
flip-flops and appear at the outputs after the positive transi-
tion of the clock input. During loading, serial data flow is
inhibited.
Shift right is accomplished synchronously with the rising
edge of the clock pulse when S0 is HIGH and S1 is LOW.
Serial data for this mode is entered at the shift-right data
input. When S0 is LOW and S1 is HIGH, data shifts left
synchronously and new data is entered at the shift-left
serial input.
Clocking of the flip-flop is inhibited when both mode control
inputs are LOW.
Features
a73 Parallel inputs and outputs
a73 Four operating modes:
Synchronous parallel load
Right shift
Left shift
Do nothing
a73 Positive edge-triggered clocking
a73 Direct overriding clear

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number Package Number Package Description
DM74LS194AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS194AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide