5-1
FAST AND LS TTL DATA
HEX D FLIP-FLOP
The LSTTL/MSI SN54/74LS174 is a high speed Hex D Flip-Flop. The
device is used primarily as a 6-bit edge-triggered storage register. The
information on the D inputs is transferred to storage during the LOW to HIGH
clock transition. The device has a Master Reset to simultaneously clear all
flip-flops. The LS174 is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all Motorola TTL families.
• Edge-Triggered D-Type Inputs
• Buffered-Positive Edge-Triggered Clock
• Asynchronous Common Reset
• Input Clamp Diodes Limit High Speed Termination Effects
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
CONNECTION DIAGRAM DIP (TOP VIEW)
14 13 12 11 10 9
1 2 3 4 5 6 7
16 15
8
V
CC
MR
Q
5
D
5
D
4
Q
4
Q
3
D
3
CP
Q
0
D
0
D
1
Q
1
D
2
Q
2
GND
PIN NAMES LOADING (Note a)
HIGH LOW
D
0
–D
5
CP
MR
Q
0
–Q
5
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
b. Temperature Ranges.
LOGIC DIAGRAM
D Q
CP
C
D
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
CP D
5
D
4
D
3
D
2
D
1
D
0
MR
14
2
6
7
34
5
9 11
12 10
13
15
D Q
CP
C
D
D Q
CP
C
D
D Q
CP
C
D
D Q
CP
C
D
D Q
CP
C
D
1
V
CC
= PIN 16
GND = PIN 8
= PIN NUMBERS
SN54/74LS174
HEX D FLIP-FLOP
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
V
CC
= PIN 16
GND = PIN 8
D
5
D
4
D
3
D
2
D
1
D
0
9
1
3 4 6 11 13 14
CP
MR
Q
2
Q
1
Q
0
Q
3
Q
4
Q
5
2 5 7 10 12 15