© 2000 Fairchild Semiconductor Corporation DS006399 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS165
8-
Bit
Par
a
ll
el
I
n
/Ser
ial
Out
put
Shif
t
Regis
t
er
s
DM74LS165
8-Bit Parallel In/Serial Output Shift Registers
General Description
This device is an 8-bit serial shift register which shifts data
in the direction of Q
A
toward Q
H
when clocked. Parallel-in
access is made available by eight individual direct data
inputs, which are enabled by a low level at the shift/load
input. These registers also feature gated clock inputs and
complementary outputs from the eighth bit.
Clocking is accomplished through a 2-input NOR gate, per-
mitting one input to be used as a clock-inhibit function.
Holding either of the clock inputs HIGH inhibits clocking,
and holding either clock input LOW with the load input
HIGH enables the other clock input. The clock-inhibit input
should be changed to the high level only while the clock
input is HIGH. Parallel loading is inhibited as long as the
load input is HIGH. Data at the parallel inputs are loaded
directly into the register on a HIGH-to-LOW transition of the
shift/load input, regardless of the logic levels on the clock,
clock inhibit, or serial inputs.
Features
a73 Complementary outputs
a73 Direct overriding (data) inputs
a73 Gated clock inputs
a73 Parallel-to-serial data conversion
a73 Typical frequency 35 MHz
a73 Typical power dissipation 105 mW

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Don't Care (any input, including transitions)
↑ = Transition from LOW-to-HIGH level
a...h = The level of steady-state input at inputs A through H, respectively.
Q
A0
, Q
B0
, Q
H0
= The level of Q
A
, Q
B
, or Q
H
, respectively, before the
indicated steady-state input conditions were established.
Q
An
, Q
Gn
= The level of Q
A
or Q
G
, respectively, before the most recent
↑ transition of the clock.
Order Number Package Number Package Description
DM74LS165M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS165WM M16B 16-Lead Small Outline Intergrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS165N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Internal
Shift/ Clock Clock Serial Parallel Outputs Output
Load Inhibit A...H Q
A
Q
B
Q
H
L X X X a...h a b h
HL LX XQ
A0
Q
B0
Q
H0
HL ↑ HXHQ
An
Q
Gn
HL ↑ LXLQ
An
Q
Gn
HH XX XQ
A0
Q
B0
Q
H0