© 2000 Fairchild Semiconductor Corporation DS006394 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS154
4-
Line
to
16-
Line
Decoder
/Demul
ti
plexer
DM74LS154
4-Line to 16-Line Decoder/Demultiplexer
General Description
Each of these 4-line-to-16-line decoders utilizes TTL cir-
cuitry to decode four binary-coded inputs into one of six-
teen mutually exclusive outputs when both the strobe
inputs, G1 and G2, are LOW. The demultiplexing function
is performed by using the 4 input lines to address the out-
put line, passing data from one of the strobe inputs with the
other strobe input LOW. When either strobe input is HIGH,
all outputs are HIGH. These demultiplexers are ideally
suited for implementing high-performance memory decod-
ers. All inputs are buffered and input clamping diodes are
provided to minimize transmission-line effects and thereby
simplify system design.
Features
a73 Decodes 4 binary-coded inputs into one of 16 mutually
exclusive outputs
a73 Performs the demultiplexing function by distributing data
from one input line to any one of 16 outputs
a73 Input clamping diodes simplify system design
a73 High fan-out, low-impedance, totem-pole outputs
a73 Typical propagation delay
3 levels of logic 23 ns
Strobe 19 ns
a73 Typical power dissipation 45 mW

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Logic Diagram
Order Number Package Number Package Description
DM74LS154WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
DM74LS154N N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide