© 2000 Fairchild Semiconductor Corporation DS006393 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS153

Dual

1-
of-
4
Line Data Sel
ector
s/Mul
t
i
p
lex
e
rs
DM74LS153
Dual 1-of-4 Line Data Selectors/Multiplexers
General Description
Each of these data selectors/multiplexers contains invert-
ers and drivers to supply fully complementary, on-chip,
binary decoding data selection to the AND-OR-invert
gates. Separate strobe inputs are provided for each of the
two four-line sections.
Features
a73 Permits multiplexing from N lines to 1 line
a73 Performs at parallel-to-serial conversion
a73 Strobe (enable) line provided for cascading
(N lines to n lines)
a73 High fan-out, low impedance, totem pole outputs
a73 Typical average propagation delay times
From data 14 ns
From strobe 19 ns
From select 22 ns
a73 Typical power dissipation 31 mW

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
Select inputs A and B are common to both sections.
H = HIGH Level
L = LOW Level
X = Don't Care
Order Number Package Number Package Description
DM74LS153M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS153N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Select
Data Inputs Strobe Output
Inputs
B A C0 C1 C2 C3 G Y
XXXXXX H L
LL L X X X L L
LL H X X X L H
LH X L X X L L
LH X H X X L H
HL X X L X L L
HL X X H X L H
HH X X X L L L
HH X X X H L H