74LS136
器件描述：Quad 2-Input Exclusive-OR Gate with Open-Collector Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：44.31KB，共4页
Sponsor by e络盟器件资料摘要：
© 2000 Fairchild Semiconductor Corporation DS009819 www.fairchildsemi.com
October 1988
Revised March 2000
DM74LS136
Quad 2-I
nput Excl
usive
-OR
Gat
e
wi
th O
p
en-Col
l
ect
or Output
s
DM74LS136
Quad 2-Input Exclusive-OR Gate with
Open-Collector Outputs
General Description
This device contains four independent gates, each of which
performs the logic exclusive-OR function.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
Order Number Package Number Package Description
DM74LS136M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS136N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Output
AB Z
LL L
LH H
HL
HH L
October 1988
Revised March 2000
DM74LS136
Quad 2-I
nput Excl
usive
-OR
Gat
e
wi
th O
p
en-Col
l
ect
or Output
s
DM74LS136
Quad 2-Input Exclusive-OR Gate with
Open-Collector Outputs
General Description
This device contains four independent gates, each of which
performs the logic exclusive-OR function.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
Order Number Package Number Package Description
DM74LS136M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS136N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Output
AB Z
LL L
LH H
HL
HH L