Figure 1. V
IN
versus V
OUT
Transfer Function
C0053
C0052
C0051
C0050
C0049
C0048
C0048 C0048C0046C0052 C0048C0046C0057C0053 C0049C0046C0050 C0049C0046C0056 C0050
C0086
C0073C0078
C0044 C0073C0078C0080C0085C0084 C0086C0079C0076C0084C0065C0071C0069 C0040C0086C0079C0076C0084C0083C0041
C0086
C0079
C0044C0032C0079C0085C0084C0080C0085C0084
C0032C0086C0079C0076
C0084
C0065C0071C0069C0032C0040C0086C0079C0076
C0084C0083C0041
C0086
C0067C0067
C0061 C0053 C0086
C0084
C0065
C0061 C0050C0053°C0067
5-212
FAST AND LS TTL DATA
QUAD 2-INPUT
SCHMITT TRIGGER NAND GATE
The SN54/74LS132 contains four 2-Input NAND Gates which accept stan-
dard TTL input signals and provide standard TTL output levels. They are ca-
pable of transforming slowly changing input signals into sharply defined, jitter-
free output signals. Additionally, they have greater noise margin than
conventional NAND Gates.
Each circuit contains a 2-input Schmitt trigger followed by a Darlington level
shifter and a phase splitter driving a TTL totem pole output. The Schmitt trigger
uses positive feedback to effectively speed-up slow input transitions, and
provide different input threshold voltages for positive and negative-going tran-
sitions. This hysteresis between the positive-going and negative-going input
thresholds (typically 800 mV) is determined internally by resistor ratios and is
essentially insensitive to temperature and supply voltage variations. As long
as one input remains at a more positive voltage than V
T+
(MAX), the gate will
respond to the transitions of the other input as shown in Figure 1.
C0049C0052 C0049C0051 C0049C0050 C0049C0049 C0049C0048 C0057
C0049 C0050 C0051 C0052 C0053 C0054
C0086
C0067C0067
C0056
C0055
C0071C0078C0068
LOGIC AND CONNECTION DIAGRAM
DIP (TOP VIEW)
SN54/74LS132
QUAD 2-INPUT
SCHMITT TRIGGER NAND GATE
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
14
1
14
1
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
14
1
D SUFFIX
SOIC
CASE 751A-02