© 2000 Fairchild Semiconductor Corporation DS006389 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS132
Quad
2-I
nput
NAND Gat
e
wit
h

Schm
i
t
t
T
r
igg
e
r
Input
DM74LS132
Quad 2-Input NAND Gate with Schmitt Trigger Input
General Description
This device contains four independent gates each of which
performs the logic NAND function. Each input has hystere-
sis which increases the noise immunity and transforms a
slowly changing input signal to a fast changing, jitter free
output.

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
Y = AB
H = HIGH Logic Level
L = LOW Logic Level
Order Number Package Number Package Description
DM74LS132M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS132SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS132N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Output
ABY
LLH
LH
HLH
HHL