74LS12
器件描述：Dual Retriggerable One-Shot with Clear and Complementary Outputs
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：96.04KB，共8页
Sponsor by e络盟器件资料摘要：
© 2000 Fairchild Semiconductor Corporation DS006386 www.fairchildsemi.com
August 1986
Revised April 2000
DM74LS123
Dual
Ret
r
i
ggerabl
e
O
n
e
-
Shot
wit
h
C
l
ear
and
Com
p
lementa
r
y
O
u
t
put
s
DM74LS123
Dual Retriggerable One-Shot
with Clear and Complementary Outputs
General Description
The DM74LS123 is a dual retriggerable monostable multi-
vibrator capable of generating output pulses from a few
nano-seconds to extremely long duration up to 100% duty
cycle. Each device has three inputs permitting the choice of
either leading edge or trailing edge triggering. Pin (A) is an
active-LOW transition trigger input and pin (B) is an active-
HIGH transition trigger input. The clear (CLR) input termi-
nates the output pulse at a predetermined time indepen-
dent of the timing components. The clear input also serves
as a trigger input when it is pulsed with a low level pulse
transition (c13). To obtain the best trouble free operation
from this device please read the operating rules as well as
the Fairchild Semiconductor one-shot application notes
carefully and observe recommendations.
Features
a73 DC triggered from active-HIGH transition or active-LOW
transition inputs
a73 Retriggerable to 100% duty cycle
a73 Compensated for V
CC
and temperature variations
a73 Triggerable from CLEAR input
a73 DTL, TTL compatible
a73 Input clamp diodes
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
H = HIGH Logic Level
L = LOW Logic Level
X = Can Be Either LOW or HIGH
↑ = Positive Going Transition
↓ = Negative Going Transition
c12 = A Positive Pulse
c13 = A Negative Pulse
Order Number Package Number Package Description
DM74LS123M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS123SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS123N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
CLEAR A B Q Q
LXXLH
XH
XXLLH
HL↑ c12c13
H ↓ H c12c13
↑ LHc12c13
August 1986
Revised April 2000
DM74LS123
Dual
Ret
r
i
ggerabl
e
O
n
e
-
Shot
wit
h
C
l
ear
and
Com
p
lementa
r
y
O
u
t
put
s
DM74LS123
Dual Retriggerable One-Shot
with Clear and Complementary Outputs
General Description
The DM74LS123 is a dual retriggerable monostable multi-
vibrator capable of generating output pulses from a few
nano-seconds to extremely long duration up to 100% duty
cycle. Each device has three inputs permitting the choice of
either leading edge or trailing edge triggering. Pin (A) is an
active-LOW transition trigger input and pin (B) is an active-
HIGH transition trigger input. The clear (CLR) input termi-
nates the output pulse at a predetermined time indepen-
dent of the timing components. The clear input also serves
as a trigger input when it is pulsed with a low level pulse
transition (c13). To obtain the best trouble free operation
from this device please read the operating rules as well as
the Fairchild Semiconductor one-shot application notes
carefully and observe recommendations.
Features
a73 DC triggered from active-HIGH transition or active-LOW
transition inputs
a73 Retriggerable to 100% duty cycle
a73 Compensated for V
CC
and temperature variations
a73 Triggerable from CLEAR input
a73 DTL, TTL compatible
a73 Input clamp diodes
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
H = HIGH Logic Level
L = LOW Logic Level
X = Can Be Either LOW or HIGH
↑ = Positive Going Transition
↓ = Negative Going Transition
c12 = A Positive Pulse
c13 = A Negative Pulse
Order Number Package Number Package Description
DM74LS123M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS123SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS123N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
CLEAR A B Q Q
LXXLH
XH
XXLLH
HL↑ c12c13
H ↓ H c12c13
↑ LHc12c13