© 2000 Fairchild Semiconductor Corporation DS006346 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS05 Hex Inver
ter
s

wi
th Open-Col
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ec
tor

Outpu
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s
DM74LS05
Hex Inverters with Open-Collector Outputs
General Description
This device contains six independent gates each of which
performs the logic INVERT function. The open-collector
outputs require external pull-up resistors for proper logical
operation.
Pull-Up Resistor Equations
Where: N
1
(I
OH
) = total maximum output high current
for all outputs tied to pull-up resistor
N
2
(I
IH
) = total maximum input high current for
all inputs tied to pull-up resistor
N
3
(I
IL
) = total maximum input low current for
all inputs tied to pull-up resistor

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
Y = A
H = HIGH Logic Level
L = LOW Logic Level
Order Number Package Number Package Description
DM74LS05M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
DM74LS05SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
DM74LS05N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Input Output
AY
LH
HL