74LCXZ16240MEA
器件描述：Low Voltage 16-Bit Inverting Buffer/Line Driver with 5V Tolerant Inputs/Outputs (Preliminary)
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：87.87KB，共8页
Sponsor by e络盟器件资料摘要：
Preliminary
© 2000 Fairchild Semiconductor Corporation DS500257 www.fairchildsemi.com
February 2000
Revised February 2000
7
4LCXZ16240 Low
V
o
lt
age 16-Bi
t Inv
e
rt
ing Buff
er/
L
ine
Dri
ver wit
h
5
V
T
o
le
rant
I
nputs/
Output
s (Pre
li
m
i
nary)
74LCXZ16240
Low Voltage 16-Bit Inverting Buffer/Line Driver with
5V Tolerant Inputs/Outputs (Preliminary)
General Description
The LCXZ16240 contains sixteen inverting buffers with 3-
STATE outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver. The device is nibble controlled. Each nibble has
separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
When V
CC
is between 0 and 1.5V, the LCXZ16240 is in the
high impedance state during power up or power down. This
places the outputs in the high impedance (Z) state prevent-
ing intermittent low impedance loading or glitching in bus
oriented applications.
The LCXZ16240 is designed for low voltage (2.7V or 3.3V)
V
CC
applications with capacity of interfacing to a 5V signal
environment.
The LCXZ16240 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
a73 5V tolerant inputs and outputs
a73 Guaranteed power up/down high impedance
a73 Supports live insertion/withdrawal
a73 2.7V–3.6V V
CC
specifications provided
a73 4.5 ns t
PD
max (V
CC
= 3.3V), 20 µA I
CC
max
a73 ±24 mA output drive (V
CC
= 3.0V)
a73 Implements patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds 500 mA
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Logic Symbol
Pin Descriptions
Order Number Package Number Package Description
74LCXZ16240MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LCXZ16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Inputs (Active LOW)
I
0
–I
15
Inputs
O
0
–O
15
Outputs
© 2000 Fairchild Semiconductor Corporation DS500257 www.fairchildsemi.com
February 2000
Revised February 2000
7
4LCXZ16240 Low
V
o
lt
age 16-Bi
t Inv
e
rt
ing Buff
er/
L
ine
Dri
ver wit
h
5
V
T
o
le
rant
I
nputs/
Output
s (Pre
li
m
i
nary)
74LCXZ16240
Low Voltage 16-Bit Inverting Buffer/Line Driver with
5V Tolerant Inputs/Outputs (Preliminary)
General Description
The LCXZ16240 contains sixteen inverting buffers with 3-
STATE outputs designed to be employed as a memory and
address driver, clock driver, or bus-oriented transmitter/
receiver. The device is nibble controlled. Each nibble has
separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
When V
CC
is between 0 and 1.5V, the LCXZ16240 is in the
high impedance state during power up or power down. This
places the outputs in the high impedance (Z) state prevent-
ing intermittent low impedance loading or glitching in bus
oriented applications.
The LCXZ16240 is designed for low voltage (2.7V or 3.3V)
V
CC
applications with capacity of interfacing to a 5V signal
environment.
The LCXZ16240 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
a73 5V tolerant inputs and outputs
a73 Guaranteed power up/down high impedance
a73 Supports live insertion/withdrawal
a73 2.7V–3.6V V
CC
specifications provided
a73 4.5 ns t
PD
max (V
CC
= 3.3V), 20 µA I
CC
max
a73 ±24 mA output drive (V
CC
= 3.0V)
a73 Implements patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds 500 mA
a73 ESD performance:
Human body model > 2000V
Machine model > 200V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Logic Symbol
Pin Descriptions
Order Number Package Number Package Description
74LCXZ16240MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
74LCXZ16240MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Pin Names Description
OE
n
Output Enable Inputs (Active LOW)
I
0
–I
15
Inputs
O
0
–O
15
Outputs