March 1995
Revised March 1999
7
4LCX86
Low V
o
l
t
age
Quad 2-I
nput

Excl
usi
ve-OR G
a
t
e
w
i
th 5V T
o
l
e
ra
nt Input
s
© 1999 Fairchild Semiconductor Corporation DS012415.prf www.fairchildsemi.com
74LCX86
Low Voltage Quad 2-Input Exclusive-OR Gate
with 5V Tolerant Inputs
General Description
The LCX86 contains four 2-input exclusive-OR gates. The
inputs tolerate voltages up to 7V allowing the interface of
5V systems to 3V systems.
The 74LCX86 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
a73 5V tolerant inputs
a73 2.3V–3.6V V
CC
specifications provided
a73 6.5 ns t
PD
max (V
CC
= 3.3V), 10 µA I
CC
max
a73 Power down high impedance inputs and outputs
a73 ±24 mA output drive (V
CC
= 3.0V)
a73 Implements patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds 500 mA
a73 ESD performance:
Machine model > 2000V
Human model > 200V

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74LCX86M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
74LCX86SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX86MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
A
0
–A
3
Inputs
B
0
–B
3
Inputs
O
0
–O
3
Outputs