© 2003 Fairchild Semiconductor Corporation DS500386 www.fairchildsemi.com
September 2000
Revised July 2003
7
4
LCX126
Low V
o
lt
age
Quad Buff
er wit
h

5V T
o
ler
a
nt

I
nputs and O
u
tput
s
74LCX126
Low Voltage Quad Buffer
with 5V Tolerant Inputs and Outputs
General Description
The LCX126 contains four independent non-inverting buff-
ers with 3-STATE outputs. Each output is disabled when
the associated output-enable (OE) input is LOW. The
inputs tolerate voltages up to 7V allowing the interface of
5V systems to 3V systems.
The 74LCX126 is fabricated with an advanced CMOS tech-
nology to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
a73 5V tolerant inputs and outputs
a73 2.3V–3.6V V
CC
specifications provided
a73 5.5 ns t
PD
max (V
CC
= 3.3V), 10 µA I
CC
max
a73 Power down high impedance inputs and outputs
a73 Supports live insertion/withdrawal (Note 1)
a73 ±24 mA output drive (V
CC
= 3.0V)
a73 Implements patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds 500 mA
a73 ESD performance:
Human body model > 2000V
Machine model > 100V
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to GND through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.

Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Pin Descriptions
Connection Diagram
Truth Table
H = HIGH Voltage Level Z = High Impedance
L = LOW Voltage Level X = Immaterial
Order Number Package Number Package Description
74LCX126M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74LCX126SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX126MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
A
n
Inputs
OE
n
Output Enable Inputs
O
n
Outputs
Inputs Output
OE
n
A
n
O
n
HLL
HHH
LXZ