© 2001 Fairchild Semiconductor Corporation DS012424 www.fairchildsemi.com
June 1998
Revised February 2001
7
4
LCX1
12
Low V
o
lt
age
Dual
J-K Negati
ve E
d
ge-T
r
i
gger
e
d Fli
p
-Fl
op w
i
th 5V T
o
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ra
nt Input
s
74LCX112
Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop
with 5V Tolerant Inputs
General Description
The LCX112 is a dual J-K flip-flop. Each flip-flop has inde-
pendent J, K, PRESET, CLEAR, and CLOCK inputs with Q,
Q outputs. These devices are edge sensitive and change
state on the negative going transition of the clock pulse.
Clear and preset are independent of the clock and accom-
plished by a low logic level on the corresponding input.
LCX devices are designed for low voltage (3.3V or 2.5)
operation with the added capability of interfacing to a 5V
signal environment.
The 74LCX112 is fabricated with advanced CMOS technol-
ogy to achieve high speed operation while maintaining
CMOS low power dissipation.
Features
a73 5V tolerant inputs
a73 2.3V–3.6V V
CC
specifications provided
a73 7.5 ns t
PD
max (V
CC
= 3.3V), 10 µA I
CC
max
a73 Power down high impedance inputs and outputs
a73 ±24 mA output drive (V
CC
= 3.0V)
a73 Implements patented noise/EMI reduction circuitry
a73 Latch-up performance exceeds 500 mA
a73 ESD performance:
Human body model > 2000V
Machine model > 2000V

Ordering Code:
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74LCX112M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74LCX112SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LCX112MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
J
1
, J
2
, K
1
, K
2
Data Inputs
CP
1
, CP
2
Clock Pulse Inputs (Active Falling Edge)
C
D1
, C
D2
Direct Clear Inputs (Active LOW)
S
D1
, S
D2
Direct Set Inputs (Active LOW)
Q
1
, Q
2
, Q
1
, Q
2
Outputs