74HC595
器件描述：8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs
器件厂商：MOTOROLA [Motorola, Inc]
文件大小：297.55KB，共10页
Sponsor by e络盟器件资料摘要：
C0077C0079C0084C0079C0082C0079C0076C0065
SEMICONDUCTOR TECHNICAL DATA
1 REV 6 Motorola, Inc. 1995
10/95
C0056C0045C0066C0105C0116 C0083C0101C0114C0105C0097C0108C0045C0073C0110C0112C0117C0116C0047C0083C0101C0114C0105C0097C0108 C0111C0114
C0080C0097C0114C0097C0108C0108C0101C0108C0045C0079C0117C0116C0112C0117C0116 C0083C0104C0105C0102C0116 C0082C0101C0103C0105C0115C0116C0101C0114
C0119C0105C0116C0104 C0076C0097C0116C0099C0104C0101C0100 C0051C0045C0083C0116C0097C0116C0101 C0079C0117C0116C0112C0117C0116C0115
High–Performance Silicon–Gate CMOS
The MC54/74HC595A is identical in pinout to the LS595. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC595A consists of an 8–bit shift register and an 8–bit D–type latch
with three–state parallel outputs. The shift register accepts serial data and
provides a serial output. The shift register also provides parallel data to the
8–bit latch. The shift register and latch have independent clock inputs. This
device also has an asynchronous reset for the shift register.
The HC595A directly interfaces with the Motorola SPI serial data port on
CMOS MPUs and MCUs.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 328 FETs or 82 Equivalent Gates
• Improvements over HC595
— Improved Propagation Delays
— 50% Lower Quiescent Power
— Improved Input Noise and Latchup Immunity
LOGIC DIAGRAM
SERIAL
DATA
INPUT
14
11
10
12
13
SHIFT
CLOCK
RESET
LATCH
CLOCK
OUTPUT
ENABLE
SHIFT
REGISTER
LATCH
15
1
2
3
4
5
6
7
9
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
SQ
H
A
V
CC
= PIN 16
GND = PIN 8
PARALLEL
DATA
OUTPUTS
SERIAL
DATA
OUTPUT
C0077C0067C0053C0052C0047C0055C0052C0072C0067C0053C0057C0053C0065
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
LATCH CLOCK
OUTPUT ENABLE
A
Q
A
V
CC
SQ
H
RESET
SHIFT CLOCK
Q
E
Q
D
Q
C
Q
B
GND
Q
H
Q
G
Q
F
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
1
16
1
16
1
16
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
SEMICONDUCTOR TECHNICAL DATA
1 REV 6 Motorola, Inc. 1995
10/95
C0056C0045C0066C0105C0116 C0083C0101C0114C0105C0097C0108C0045C0073C0110C0112C0117C0116C0047C0083C0101C0114C0105C0097C0108 C0111C0114
C0080C0097C0114C0097C0108C0108C0101C0108C0045C0079C0117C0116C0112C0117C0116 C0083C0104C0105C0102C0116 C0082C0101C0103C0105C0115C0116C0101C0114
C0119C0105C0116C0104 C0076C0097C0116C0099C0104C0101C0100 C0051C0045C0083C0116C0097C0116C0101 C0079C0117C0116C0112C0117C0116C0115
High–Performance Silicon–Gate CMOS
The MC54/74HC595A is identical in pinout to the LS595. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC595A consists of an 8–bit shift register and an 8–bit D–type latch
with three–state parallel outputs. The shift register accepts serial data and
provides a serial output. The shift register also provides parallel data to the
8–bit latch. The shift register and latch have independent clock inputs. This
device also has an asynchronous reset for the shift register.
The HC595A directly interfaces with the Motorola SPI serial data port on
CMOS MPUs and MCUs.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 328 FETs or 82 Equivalent Gates
• Improvements over HC595
— Improved Propagation Delays
— 50% Lower Quiescent Power
— Improved Input Noise and Latchup Immunity
LOGIC DIAGRAM
SERIAL
DATA
INPUT
14
11
10
12
13
SHIFT
CLOCK
RESET
LATCH
CLOCK
OUTPUT
ENABLE
SHIFT
REGISTER
LATCH
15
1
2
3
4
5
6
7
9
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
SQ
H
A
V
CC
= PIN 16
GND = PIN 8
PARALLEL
DATA
OUTPUTS
SERIAL
DATA
OUTPUT
C0077C0067C0053C0052C0047C0055C0052C0072C0067C0053C0057C0053C0065
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
LATCH CLOCK
OUTPUT ENABLE
A
Q
A
V
CC
SQ
H
RESET
SHIFT CLOCK
Q
E
Q
D
Q
C
Q
B
GND
Q
H
Q
G
Q
F
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
1
16
1
16
1
16
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16