74HC541
器件描述：Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：89.66KB，共6页
Sponsor by e络盟器件资料摘要：
September 1983
Revised February 1999
MM74HC540
• MM74HC541 I
n
ver
ti
ng Oct
a
l
3-ST
A
T
E Buf
f
e
r
•
Octal
3-
ST
A
T
E
Buff
er
© 1999 Fairchild Semiconductor Corporation DS005341.prf www.fairchildsemi.com
MM74HC540 • MM74HC541
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Description
The MM74HC540 and MM74HC541 3-STATE buffers uti-
lize advanced silicon-gate CMOS technology. They pos-
sess high drive current outputs which enable high speed
operation even when driving large bus capacitances.
These circuits achieve speeds comparable to low power
Schottky devices, while retaining the advantage of CMOS
circuitry, i.e., high noise immunity, and low power consump-
tion. Both devices have a fanout of 15 LS-TTL equivalent
inputs.
The MM74HC540 is an inverting buffer and the
MM74HC541 is a non-inverting buffer. The 3-STATE con-
trol gate operates as a two-input NOR such that if either G1
or G2 are HIGH, all eight outputs are in the high-imped-
ance state.
In order to enhance PC board layout, the MM74HC540 and
MM74HC541 offers a pinout having inputs and outputs on
opposite sides of the package. All inputs are protected from
damage due to static discharge by diodes to V
CC
and
ground.
Features
a73 Typical propagation delay: 12 ns
a73 3-STATE outputs for connection to system buses
a73 Wide power supply range: 2–6V
a73 Low quiescent current: 80 µA maximum (74HC Series)
a73 Output current: 6 mA
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HC540
Top View
MM74HC541
Order Number Package Number Package Description
MM74HC540WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC540SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC540MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC540N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HC541WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC541N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Revised February 1999
MM74HC540
• MM74HC541 I
n
ver
ti
ng Oct
a
l
3-ST
A
T
E Buf
f
e
r
•
Octal
3-
ST
A
T
E
Buff
er
© 1999 Fairchild Semiconductor Corporation DS005341.prf www.fairchildsemi.com
MM74HC540 • MM74HC541
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Description
The MM74HC540 and MM74HC541 3-STATE buffers uti-
lize advanced silicon-gate CMOS technology. They pos-
sess high drive current outputs which enable high speed
operation even when driving large bus capacitances.
These circuits achieve speeds comparable to low power
Schottky devices, while retaining the advantage of CMOS
circuitry, i.e., high noise immunity, and low power consump-
tion. Both devices have a fanout of 15 LS-TTL equivalent
inputs.
The MM74HC540 is an inverting buffer and the
MM74HC541 is a non-inverting buffer. The 3-STATE con-
trol gate operates as a two-input NOR such that if either G1
or G2 are HIGH, all eight outputs are in the high-imped-
ance state.
In order to enhance PC board layout, the MM74HC540 and
MM74HC541 offers a pinout having inputs and outputs on
opposite sides of the package. All inputs are protected from
damage due to static discharge by diodes to V
CC
and
ground.
Features
a73 Typical propagation delay: 12 ns
a73 3-STATE outputs for connection to system buses
a73 Wide power supply range: 2–6V
a73 Low quiescent current: 80 µA maximum (74HC Series)
a73 Output current: 6 mA
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HC540
Top View
MM74HC541
Order Number Package Number Package Description
MM74HC540WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC540SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC540MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC540N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HC541WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC541SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC541MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC541N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide