74HC4538
器件描述：Dual Precision Monostable Multivibrator(Retriggerable, Resettable)
器件厂商：MOTOROLA [Motorola, Inc]
文件大小：368.87KB，共13页
Sponsor by e络盟器件资料摘要：
C0077C0079C0084C0079C0082C0079C0076C0065
SEMICONDUCTOR TECHNICAL DATA
3–1 REV 6 Motorola, Inc. 1995
10/95
C0068C0117C0097C0108 C0080C0114C0101C0099C0105C0115C0105C0111C0110
C0077C0111C0110C0111C0115C0116C0097C0098C0108C0101 C0077C0117C0108C0116C0105C0118C0105C0098C0114C0097C0116C0111C0114
C0040C0082C0101C0116C0114C0105C0103C0103C0101C0114C0097C0098C0108C0101C0044 C0082C0101C0115C0101C0116C0116C0097C0098C0108C0101C0041
The MC54/74HC4538A is identical in pinout to the MC14538B. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This dual monostable multivibrator may be triggered by either the positive
or the negative edge of an input pulse, and produces a precision output
pulse over a wide range of pulse widths. Because the device has conditioned
trigger inputs, there are no trigger–input rise and fall time restrictions. The
output pulse width is determined by the external timing components, R
x
and
C
x
. The device has a reset function which forces the Q output low and the Q
output high, regardless of the state of the output pulse circuitry.
• Unlimited Rise and Fall Times Allowed on the Trigger Inputs
• Output Pulse is Independent of the Trigger Pulse Width
• ± 10% Guaranteed Pulse Width Variation from Part to Part (Using the
Same Test Jig)
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 3.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 145 FETs or 36 Equivalent Gates
LOGIC DIAGRAM
PIN 16 = V
CC
PIN 8 = GND
R
X
AND C
X
ARE EXTERNAL COMPONENTS
PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND
C
X
1 R
X
1
V
CC
Q1
RESET 1
B1
A1
TRIGGER
INPUTS
Q1
1 2
4
5
3
6
7
C
X
2 R
X
2
V
CC
Q2
RESET 2
B2
A2
TRIGGER
INPUTS
Q2
15 14
12
11
13
10
9
C0077C0067C0053C0052C0047C0055C0052C0072C0067C0052C0053C0051C0056C0065
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
A2
RESET 2
C
X
2/R
X
2
GND
V
CC
Q2
Q2
B2
A1
RESET 1
C
X
1/R
X
1
GND
GND
Q1
Q1
B1
FUNCTION TABLE
Inputs Outputs
Reset A B Q Q
H H
H L
H X L Not Triggered
H H X Not Triggered
H L,H, H Not Triggered
H L L,H, Not Triggered
L X X L H
X X Not Triggered
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXXAJ
MC74HCXXXXAN
MC74HCXXXXAD
Ceramic
Plastic
SOIC
1
16
1
16
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
SEMICONDUCTOR TECHNICAL DATA
3–1 REV 6 Motorola, Inc. 1995
10/95
C0068C0117C0097C0108 C0080C0114C0101C0099C0105C0115C0105C0111C0110
C0077C0111C0110C0111C0115C0116C0097C0098C0108C0101 C0077C0117C0108C0116C0105C0118C0105C0098C0114C0097C0116C0111C0114
C0040C0082C0101C0116C0114C0105C0103C0103C0101C0114C0097C0098C0108C0101C0044 C0082C0101C0115C0101C0116C0116C0097C0098C0108C0101C0041
The MC54/74HC4538A is identical in pinout to the MC14538B. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This dual monostable multivibrator may be triggered by either the positive
or the negative edge of an input pulse, and produces a precision output
pulse over a wide range of pulse widths. Because the device has conditioned
trigger inputs, there are no trigger–input rise and fall time restrictions. The
output pulse width is determined by the external timing components, R
x
and
C
x
. The device has a reset function which forces the Q output low and the Q
output high, regardless of the state of the output pulse circuitry.
• Unlimited Rise and Fall Times Allowed on the Trigger Inputs
• Output Pulse is Independent of the Trigger Pulse Width
• ± 10% Guaranteed Pulse Width Variation from Part to Part (Using the
Same Test Jig)
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 3.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 145 FETs or 36 Equivalent Gates
LOGIC DIAGRAM
PIN 16 = V
CC
PIN 8 = GND
R
X
AND C
X
ARE EXTERNAL COMPONENTS
PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND
C
X
1 R
X
1
V
CC
Q1
RESET 1
B1
A1
TRIGGER
INPUTS
Q1
1 2
4
5
3
6
7
C
X
2 R
X
2
V
CC
Q2
RESET 2
B2
A2
TRIGGER
INPUTS
Q2
15 14
12
11
13
10
9
C0077C0067C0053C0052C0047C0055C0052C0072C0067C0052C0053C0051C0056C0065
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
A2
RESET 2
C
X
2/R
X
2
GND
V
CC
Q2
Q2
B2
A1
RESET 1
C
X
1/R
X
1
GND
GND
Q1
Q1
B1
FUNCTION TABLE
Inputs Outputs
Reset A B Q Q
H H
H L
H X L Not Triggered
H H X Not Triggered
H L,H, H Not Triggered
H L L,H, Not Triggered
L X X L H
X X Not Triggered
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXXAJ
MC74HCXXXXAN
MC74HCXXXXAD
Ceramic
Plastic
SOIC
1
16
1
16
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16