1
Data sheet acquired from Harris Semiconductor
SCHS211
Features
• Buffered Inputs
• Separate Serial Outputs Synchronous to Both
Positive and Negative Clock Edges For Cascading
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤ 1µA at V
OL
, V
OH
Pinout
CD74HC4094, CD74HCT4094
(PDIP, SOIC)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
STROBE
DATA
CP
Q
0
Q
1
Q
2
GND
Q
3
V
CC
Q
4
Q
5
Q
6
Q
7
QS
2
QS
1
OE
November 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
File Number 1779.1
CD74HC4094,
CD74HCT4094
High Speed CMOS Logic
8-Stage Shift and Store Bus Register, Three-State
[ /Title
(CD74H
C4094,
CD74H
CT4094
)
/Sub-
ject
(High
Speed
CMOS
Logic 8-