1
Data sheet acquired from Harris Semiconductor
SCHS210
Features
• Buffered Inputs
• Typical Propagation Delay: 8ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤ 1µA at V
OL
, V
OH
Description
The Harris CD74HC4075, CD74HCT4075 logic gates utilize
silicon-gate CMOS technology to achieve operating speeds
similar to LSTTL gates with the low power consumption of
standard CMOS integrated circuits. All devices have the
ability to drive 10 LSTTL loads. The 74HCT logic family is
functionally pin compatible with the standard 74LS logic
family.
Pinout
CD74HC4075, CD74HCT4075
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER TEMP. RANGE (
o
C) PACKAGE
PKG.
NO.
CD74HC4075E -55 to 125 14 Ld PDIP E14.3
CD74HC4075E -55 to 125 14 Ld PDIP E14.3
CD74HC4075M -55 to 125 14 Ld SOIC M14.15
CD74HC4075M -55 to 125 14 Ld SOIC M14.15
CD54HC4075H -55 to 125 Die
CD54HCT4075H -55 to 125 Die
CD54HC4075W -55 to 125 Wafer
CD54HCT4075W -55 to 125 Wafer
NOTE: When ordering, use the entire part number. Add the suffix 96
to obtain the variant in the tape and reel.
2A
2B
1A
1B
1C
1C
GND
V
CC
3C
3B
3A
3Y
2Y
2C
1
2
3
4
5
6
7
14
13
12
11
10
9
8
August 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
CD74HC4075,
CD74HCT4075
High Speed CMOS Logic
Triple 3-Input OR Gate
File Number 1778.1
[ /Title
(CD74H
C4075,
CD74H
CT4075)
/Subject
(High
Speed
CMOS
Logic
Triple 3-
Input