M54HC148
M74HC148
October 1992
8 TO 3 LINE PRIORITY ENCODER
B1R
(Plastic Package)
ORDER CODES :
M54HC148F1R M74HC148M1R
M74HC148B1R M74HC148C1R
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
DESCRIPTION
.HIGH SPEED
tPD = 15 ns (TYP.) AT VCC =5V
.LOW POWER DISSIPATION
I
CC
=4µA (MAX.) AT T
A
=25°C
.HIGH NOISE IMMUNITY
VNIH =VNIL =28%VCC (MIN.)
.OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.SYMMETRICAL OUTPUT IMPEDANCE
I
OH
 =IOL = 4 mA (MIN.)
.BALANCED PROPAGATION DELAYS
t
PLH
=t
PHL
.WIDE OPERATING VOLTAGE RANGE
VCC (OPR) = 2 V TO 6 V
.PIN AND FUNCTION COMPATIBLE
WITH 54/74LS148
The M54/74HC148 is a high speed CMOS 8-TO-3
LINE PRIORITY ENCODER fabricated in silicon
gate C
2
MOS technology.
It has the same high speed performance for LSTTL
combined with true CMOS low power consumption.
The M54/74HC148 encodes eight data lines to
three-line (4-2-1) binary (octal). Cascading circuitry
(enable input EI and enable output EO) has been
provided to allow octal expansion without the need
for external circuitry. Data inputs are active at the
low logic level.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
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