October 1987
Revised February 1999
MM74HC148 8-3 Li
ne
Pr
ior
i
t
y

Encode
r
© 1999 Fairchild Semiconductor Corporation DS009390.prf www.fairchildsemi.com
MM74HC148
8-3 Line Priority Encoder
General Description
The MM74HC148 priority encoder utilizes advanced sili-
con-gate CMOS technology. It has the high noise immunity
and low power consumption typical of CMOS circuits, as
well as the speeds and output drive similar to LB-TTL.
This priority encoder accepts 8 input request lines 0–7 and
outputs 3 lines A0–A2. The priority encoding ensures that
only the highest order data line is encoded. Cascading cir-
cuitry (enable input EI and enable output EO) has been
provided to allow octal expansion without the need for
external circuitry. All data inputs and outputs are active at
the low logic level.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
CC
and ground.
Features
a73 Typical propagation delay: 13 ns
a73 Wide supply voltage range: 2V–6V

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC and TSSOP
Truth Table
H = HIGH
L = LOW
X = Irrelevant
Order Number Package Number Package Description
MM74HC148M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC148MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC148N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Inputs Outputs
EI01234567A2A1A0GSEO
HXXXXXXXX H H H H H
L HHHHHHHH H H H H L
L XXXXXXXL L L L L H
L XXXXXXLH L L H L H
L XXXXXLHH L H L L H
L XXXXLHHH L H H L H
L XXXLHHHH H L L L H
L XXLHHHHH H L H L H
L XLHHHHHH H H L L H
L LHHHHHHH H H H L H