© 2000 Fairchild Semiconductor Corporation DS006382 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS1
1
2
A
Dual

Negat
ive
-
Edge-
T
r
i
ggered Maste
r
-Sl
ave J-K Fli
p
-
F
lop wit
h

Pr
eset,

Cl
ear
, and
Compl
e
m
ent
ary
Out
puts
DM74LS112A
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent negative-edge-trig-
gered J-K flip-flops with complementary outputs. The J and
K data is processed by the flip-flop on the falling edge of
the clock pulse. The clock triggering occurs at a voltage
level and is not directly related to the transition time of the
falling edge of the clock pulse. Data on the J and K inputs
may be changed while the clock is HIGH or LOW without
affecting the outputs as long as the setup and hold times
are not violated. A low logic level on the preset or clear
inputs will set or reset the outputs regardless of the logic
levels of the other inputs.

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Function Table
H = HIGH Logic Level
L = LOW Logic Level
X = Either LOW or HIGH Logic Level
↓ = Negative Going Edge of Pulse
Q
0
= The output logic level before the indicated input conditions were
established.
Toggle = Each output changes to the complement of its previous level on
each falling edge of the clock pulse.
Note 1: This configuration is nonstable; that is, it will not persist when
preset and/or clear inputs return to their inactive (HIGH) level.
Order Number Package Number Package Description
DM74KS112AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS112AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Inputs Outputs
PR CLR CLK J K Q Q
LHXXX H L
HLXXX L H
L L X X X H (Note 1) H (Note 1)
HH↓ LL Q
0
Q
0
HH↓ HL H L
HH↓ LH L H
HH↓ HH Togle
HHHXX Q
0
Q
0