74LS112
器件描述：DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
器件厂商：MOTOROLA [Motorola, Inc]
文件大小：147.33KB，共4页
Sponsor by e络盟器件资料摘要：
5-185
FAST AND LS TTL DATA
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54/74LS112A dual JK flip-flop features individual J, K, clock, and
asynchronous set and clear inputs to each flip-flop. When the clock goes
HIGH, the inputs are enabled and data will be accepted. The logic level of the
J and K inputs may be allowed to change when the clock pulse is HIGH and
the bistable will perform according to the truth table as long as minimum set-up
and hold time are observed. Input data is transferred to the outputs on the
negative-going edge of the clock pulse.
LOGIC DIAGRAM (Each Flip-Flop)
C0081
C0053C0040C0057C0041
C0067C0076C0069C0065C0082 C0040C0067
C0068
C0041
C0049C0053C0040C0049C0052C0041
C0074
C0051C0040C0049C0049C0041
C0081
C0054C0040C0055C0041
C0083C0069C0084 C0040C0083
C0068
C0041
C0052C0040C0049C0048C0041
C0075
C0050C0040C0049C0050C0041
C0049C0040C0049C0051C0041
C0067C0076C0079C0067C0075 C0040C0067C0080C0041
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS OUTPUTS
TING MODE
S
D
C
D
J K Q Q
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
L
H
L
H
H
H
H
H
L
L
H
H
H
H
X
X
X
h
l
h
l
X
X
X
h
h
l
l
H
L
H
q
L
H
q
L
H
H
q
H
L
q
* Both outputs will be HIGH while both S
D
and C
D
are LOW, but the output states
are unpredictable if S
D
and C
D
go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
SN54/74LS112A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
C0086
C0067C0067
C0061 C0080C0073C0078 C0049C0054
C0071C0078C0068 C0061 C0080C0073C0078 C0056
C0052
C0051
C0049
C0050
C0049C0053
C0053
C0054
C0083
C0068
C0074
C0067C0080
C0075
C0067
C0068
C0081
C0081
C0049C0048
C0049C0049
C0057
C0049C0051
C0049C0050
C0049C0052
C0055
C0083
C0068
C0074
C0067C0080
C0075
C0067
C0068
C0081
C0081
FAST AND LS TTL DATA
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54/74LS112A dual JK flip-flop features individual J, K, clock, and
asynchronous set and clear inputs to each flip-flop. When the clock goes
HIGH, the inputs are enabled and data will be accepted. The logic level of the
J and K inputs may be allowed to change when the clock pulse is HIGH and
the bistable will perform according to the truth table as long as minimum set-up
and hold time are observed. Input data is transferred to the outputs on the
negative-going edge of the clock pulse.
LOGIC DIAGRAM (Each Flip-Flop)
C0081
C0053C0040C0057C0041
C0067C0076C0069C0065C0082 C0040C0067
C0068
C0041
C0049C0053C0040C0049C0052C0041
C0074
C0051C0040C0049C0049C0041
C0081
C0054C0040C0055C0041
C0083C0069C0084 C0040C0083
C0068
C0041
C0052C0040C0049C0048C0041
C0075
C0050C0040C0049C0050C0041
C0049C0040C0049C0051C0041
C0067C0076C0079C0067C0075 C0040C0067C0080C0041
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS OUTPUTS
TING MODE
S
D
C
D
J K Q Q
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
L
H
L
H
H
H
H
H
L
L
H
H
H
H
X
X
X
h
l
h
l
X
X
X
h
h
l
l
H
L
H
q
L
H
q
L
H
H
q
H
L
q
* Both outputs will be HIGH while both S
D
and C
D
are LOW, but the output states
are unpredictable if S
D
and C
D
go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
SN54/74LS112A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
C0086
C0067C0067
C0061 C0080C0073C0078 C0049C0054
C0071C0078C0068 C0061 C0080C0073C0078 C0056
C0052
C0051
C0049
C0050
C0049C0053
C0053
C0054
C0083
C0068
C0074
C0067C0080
C0075
C0067
C0068
C0081
C0081
C0049C0048
C0049C0049
C0057
C0049C0051
C0049C0050
C0049C0052
C0055
C0083
C0068
C0074
C0067C0080
C0075
C0067
C0068
C0081
C0081