74FR900
器件描述：9-Bit, 3-Port Latchable Datapath Multiplexer
器件厂商：FAIRCHILD [Fairchild Semiconductor]
文件大小：46.65KB，共6页
Sponsor by e络盟器件资料摘要：
© 1999 Fairchild Semiconductor Corporation DS010990 www.fairchildsemi.com
May 1992
Revised August 1999
7
4FR900 9
-
Bit
,
3-
Port
Lat
chabl
e Dat
apat
h Mult
i
p
lexer
74FR900
9-Bit, 3-Port Latchable Datapath Multiplexer
General Description
The 74FR900 is a data bus multiplexer routing any of three
9-bit ports to any other one of the three ports. Readback of
data latched from any port onto itself is also possible. The
74FR900 maintains separate control of all latch-enable,
output enable and select inputs for maximum flexibility.
PINV allows inversion of the data from the C
8
to A
8
or B
8
path. This is useful for control of the parity bit in systems
diagnostics.
Fairchild’s 74FR25900 includes 25Ω resistors in series with
port A and B outputs. Resistors minimize undershoot and
ringing which may damage or corrupt sensitive device
inputs driven by these ports.
Features
a73 9-bit data ports for systems carrying parity bits
a73 Readback capability for system self checks.
a73 Independent control lines for maximum flexibility
a73 Guaranteed multiple output switching and 250 pF load
delays
a73 Outputs optimized for dynamic bus drive capability
a73 PINV parity control facilitates system diagnostics
a73 FR25900 resistor option for driving MOS inputs such as
DRAM arrays
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Description
Connection Diagram
Order Number Package Number Package Description
74FR900SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Pin Names Description
LExx
Latch Enable Inputs
OE
x
Output Enable Inputs
PINV Parity Invert Input
S
0
, S
1
Select Inputs
A
0
–A
8
Port A Inputs or 3-STATE Outputs
B
0
–B
8
Port B Inputs or 3-STATE Outputs
C
0
–C
8
Port C Inputs or 3-STATE Outputs
May 1992
Revised August 1999
7
4FR900 9
-
Bit
,
3-
Port
Lat
chabl
e Dat
apat
h Mult
i
p
lexer
74FR900
9-Bit, 3-Port Latchable Datapath Multiplexer
General Description
The 74FR900 is a data bus multiplexer routing any of three
9-bit ports to any other one of the three ports. Readback of
data latched from any port onto itself is also possible. The
74FR900 maintains separate control of all latch-enable,
output enable and select inputs for maximum flexibility.
PINV allows inversion of the data from the C
8
to A
8
or B
8
path. This is useful for control of the parity bit in systems
diagnostics.
Fairchild’s 74FR25900 includes 25Ω resistors in series with
port A and B outputs. Resistors minimize undershoot and
ringing which may damage or corrupt sensitive device
inputs driven by these ports.
Features
a73 9-bit data ports for systems carrying parity bits
a73 Readback capability for system self checks.
a73 Independent control lines for maximum flexibility
a73 Guaranteed multiple output switching and 250 pF load
delays
a73 Outputs optimized for dynamic bus drive capability
a73 PINV parity control facilitates system diagnostics
a73 FR25900 resistor option for driving MOS inputs such as
DRAM arrays
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Pin Description
Connection Diagram
Order Number Package Number Package Description
74FR900SSC MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
Pin Names Description
LExx
Latch Enable Inputs
OE
x
Output Enable Inputs
PINV Parity Invert Input
S
0
, S
1
Select Inputs
A
0
–A
8
Port A Inputs or 3-STATE Outputs
B
0
–B
8
Port B Inputs or 3-STATE Outputs
C
0
–C
8
Port C Inputs or 3-STATE Outputs