© 1999 Fairchild Semiconductor Corporation DS010901 www.fairchildsemi.com
October 1991
Revised August 1999
7
4FR240 Oct
a
l
Buff
er/
L
i
ne Dr
iver
wi
th
3-ST
A
T
E Out
puts
74FR240
Octal Buffer/Line Driver with 3-STATE Outputs
General Description
The 74FR240 is an inverting octal buffer and line driver
designed to be employed as memory and address driver,
clock driver and bus oriented transmitter or receiver.
Features
a73 3-STATE outputs drive bus lines or buffer memory
address registers
a73 Outputs sink 64 mA and source 15 mA
a73 Guaranteed pin-to-pin skew

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram Pin Descriptions
Truth Tables
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Order Number Package Number Package Description
74FR240SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74FR240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74FR240PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
OE
1
, OE
2
Output Enable Input (Active-LOW)
I
0
–I
7
Inputs
O
0
–O
7
Outputs
Inputs Outputs
OE
1
I
n
(Pins 12, 14, 16, 18)
LL H
LH L
HX Z
Inputs Outputs
OE
2
I
n
(Pins 3, 5, 7, 9)
LL H
LH L
HX Z