© 1999 Fairchild Semiconductor Corporation DS010977 www.fairchildsemi.com
March 1992
Revised August 1999
7
4FR74
• 74FR1074 Dual D-T
ype

Fl
ip-
F
lop
74FR74 • 74FR1074
Dual D-Type Flip-Flop
General Description
The 74FR74 and 74FR1074 are dual D-type flip-flops with
true and complement (Q/Q) outputs. On the 74FR74, data
at the D inputs is transferred to the outputs on the rising
edge of the clock input (CP
n
). The 74FR1074 is the nega-
tive edge triggered version of this device. Both parts fea-
ture asynchronous clear (C
Dn
) and set (S
Dn
) inputs which
are low level enabled.
Features
a73 74FR74 is pin-for-pin compatible with the 74F74
a73 True 150 MHz f
MAX
capability on 74FR74
a73 Outputs sink 24 mA and source 24 mA
a73 Guaranteed pin-to-pin skew specifications

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
74FR74 74FR1074
Order Number Package Number Package Description
74FR74SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74FR74PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74FR1074SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74FR1074PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide