© 1999 Fairchild Semiconductor Corporation DS009599 www.fairchildsemi.com
March 1988
Revised August 1999
7
4F841 10-Bi
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74F841
10-Bit Transparent Latch
General Description
The 74F841 bus interface latch is designed to eliminate the
extra packages required to buffer existing latches and pro-
vide extra data width for wider address/data paths or buses
carrying parity. The 74F841 is a 10-bit transparent latch, a
10-bit version of the 74F373.
Features
a73 3-STATE output

Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
Order Number Package Number Package Description
74F841SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F841SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide