April 1988
Revised March 1999
7
4F64 4
-
2-
3-2-
Inp
u
t
AN
D-
OR
-
I
nvert
Gat
e
© 1999 Fairchild Semiconductor Corporation DS009467.prf www.fairchildsemi.com
74F64
4-2-3-2-Input AND-OR-Invert Gate
General Description
This device contains gates configured to perform a 4-2-3-2
input AND-OR-INVERT function.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Unit Loading/Fan Out
Order Number Package Number Package Description
74F64SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F64SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F64PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
U.L. Input I
IH
/I
IL
HIGH/LOW Output I
OH
/I
OL
A
n
, B
n
, C
n
, D
n
Inputs 1.0/1.0 20 µA/−0.6 mA
O Output 50/33.3 −1 mA/20 mA