Philips Semiconductors Product specification
74F539Dual 1-of-4 decoder (3-State)
11990 Feb 23 853–1274 98905
DESCRIPTION
The 74F539 contains two independent decoders. Each accepts two
address (A0 - A1) input signals and decodes them to select one of
four mutually exclusive outputs. A Polarity control (P) input
determines whether the outputs are active Low (P=H) or active High
(P=L). An active-Low Enable (E) is available for data demultiplexing.
Data is routed to the selected output in non-inverted or inverted form
in the active-Low mode or inverted form in the active-High mode. A
High signal on the Output Enable (OEn) input forces the 3-State
outputs to the high impedance state.
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F539 7.5ns 40mA
ORDERING INFORMATION
DESCRIPTION COMMERCIAL RANGE
V
CC
= 5V ±10%, T
amb
= 0°C to +70°C
20-Pin Plastic DIP N74F539N
20-Pin Plastic SOL N74F539D
PIN CONFIGURATION
20
19
18
17
16
15
14
13
12
10 11
9
8
7
6
5
4
3
2
1
V
CC
Q3b
A1b
A0b
OEa
Pa
Q0a
Q1a
Q2b
Q1b
Q0b
A0a
A1a
Q3a
Q2a
GND
Eb
Ea
OEb
Pb
SF01013
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74F(U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0a - A1a Decoder A Address inputs 1.0/1.0 20µA/0.6mA
A0b - A1b Decoder B Address inputs 1.0/1.0 20µA/0.6mA
Ea, Eb Enable inputs (active Low) 1.0/1.0 20µA/0.6mA
OEa, OEb Output Enable inputs (active Low) 1.0/1.0 20µA/0.6mA
Pa, Pb Polarity control inputs 1.0/1.0 20µA/0.6mA
Q0a–Q3a Decoder A Data outputs 150/40 3.0mA/24mA
Q0b–Q3b Decoder A Data outputs 150/40 3.0mA/24mA
NOTE: One (1.0) FAST Unit Load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
6717
V
CC
= Pin 20
GND = Pin 10
12 11 9 8 3 2 1 19
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b
Pa
Ea
OEa
Pb
Eb
OEb
13
15
14
4
16
5
A0a A1a A0b
SF01014
18
A1b
LOGIC SYMBOL (IEEE/IEC)
17
18
16
14
19
DMUX
1
2
3
5
0,4
0
1
G
0
3
SF01015
8
9
11
12
1,4
2,4
3,4
6
7
15
4
N4
EN
13