April 1988
Revised March 1999
7
4F37
Quad T
w
o-I
nput NAND
Buf
f
er
© 1999 Fairchild Semiconductor Corporation DS009464.prf www.fairchildsemi.com
74F37
Quad Two-Input NAND Buffer
General Description
This device contains four independent gates, each of which
performs the logic NAND function.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Unit Loading/Fan Out
Connection Diagram
Function Table
H = HIGH Voltage Level
L = LOW Voltage Level
Order Number Package Number Package Description
74F37SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
74F37SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F37PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Pin Names Description
U.L. Input I
IH
/I
IL
HIGH/LOW Output I
OH
/I
OL
A
n
, B
n
Inputs 1.0/2.0 20 µA/−1.2 mA
O
n
Outputs 600/106.6 (80) −12 mA/64 mA
(48 mA)
Inputs Output
ABO
LLH
LH
HLH
HHL